Integrated circuit (IC) designs typically undergo extensive simulation before being implemented in silicon. These simulations are generally based on a defined set of parameters that are intended to provide a reasonable characterization of the actual behavior of the devices in the final IC. Unfortunately, as IC dimensions continue to shrink, physical effects not captured by traditional simulation parameters can significantly affect IC performance.
For example, for sub-0.25 μm processes, shallow trench isolation (STI) has begun to replace the traditional local oxidation of silicon (LOCOS) structures used to separate transistors. FIG. 1 shows a metal-oxide-semiconductor (MOS) transistor 100 that includes a source 141 and a drain 142 formed in an active region 120 in a substrate 190, a gate oxide 150 formed over a channel region 130 between source 141 and drain 142, and a gate 160 formed over gate oxide 150. Compact STI oxide structures 111 and 112 isolate transistor 100 from neighboring devices.
STI improves over LOCOS by providing more efficient and more controllable isolation structures that allow substantially greater transistor packing density. However, the nature of the STI formation processes can create localized stress in the diffusion region between STI structures. This particular physical effect, sometimes referred to as “STI stress,” can significantly impact the current drive of a transistor (i.e., the current carrying characteristics of the transistor, such as saturation current) that is isolated by STI structures. STI stress is a highly complex physical effect that can either increase or decrease carrier mobility in the active region of a transistor, thereby increasing or decreasing, respectively, the current drive of the transistor.
FIG. 2 shows an IC layout 200 that includes transistors 201, 202, and 203. Transistor 201 includes an active region 221 and an overlying gate 261 that defines a channel region 231 in active region 221. Transistor 201 is isolated by STI structures 211 and 212. Transistor 202 includes an active region 222 and an overlying gate 262 that defines a channel region 232 in active region 222. Transistor 202 is isolated by STI structures 212 and 213. Finally, transistor 203 includes an active region 223 and an overlying gate 263 that defines a channel region 233 in active region 223. Transistor 203 is isolated by STI structures 213 and 214.
Typically, the only physical characteristics used to model the behavior of a transistor are channel length and channel width, which, in conjunction with various process parameters (dopant level, etc.) (also called a process recipe), are used in simulations to calculate the expected current drive for that transistor. For example, channel regions 231, 232, and 233 of transistors 201, 202, and 203, respectively, have channel lengths L1, L2, and L3, respectively, and channel widths W1, W2, and W3, respectively. When channel lengths L1, L2, and L3 are all the same, and channel widths W1, W2, and W3 are all the same, transistors 201, 202, and 203 will be modeled for simulation as having equal current drives.
Unfortunately, STI stresses can degrade the accuracy of such simulations. STI stress is related not to the dimensions of the channel itself, but rather to the “channel spacing” of the transistor, i.e., the spacing between the channel (or gate) of the transistor and the adjacent STI structures. Note that since the channel (and gate) of a transistor is typically centered between STI structures, the channel spacing of a transistor can be taken with reference to either adjacent STI structure. For example, in FIG. 2, channel spacings D1, D2, and D3 determine the degree of STI stress present in transistors 201, 202, and 203, respectively. Therefore, even though they have similar channel dimensions, transistors 201, 202, and 203 can have significantly different current drives due to STI stress variations.
The precise effects of physical effects such as STI stress are closely tied to the particular process recipe being used. Therefore, any efforts to correct or compensate for physical effects must be tailored to a specific process. However, because process development is typically performed in parallel with IC design to minimize time to production, incorporating physical effects into early simulations is generally not possible. The process details needed to determine the exact nature of the physical effects are not yet known at the stage of early simulation. Consequently, conventional physical effect compensation techniques can be extremely expensive and time consuming.
For example, FIG. 3 shows a flow diagram of a conventional IC design flow (along with a concurrent process development flow). The IC design flow begins with a logic design step 310, in which an IC specification is defined and an initial functional design F_initial (i.e., a schematic or hardware description language (HDL) design) based on that IC specification is created. Concurrently, the process recipe(s) for production of the final ICs are defined and refined in a time-consuming process development step 390. Note the relative positions of process development step 390 and IC design flow steps 310–380 does not indicate that the steps necessarily begin and end at the same time, but rather merely indicates that the IC design flow and the process development flow progress along parallel tracks.
Once initial functional design F_initial is defined, it is modeled and tested in a logic verification step 320 to determine whether the functional design is correct. The operation of the functional design is simulated by applying a range of inputs to the functional design, and comparing the resulting outputs with a set of expected outputs. The functional design can then be adjusted in response to any unexpected output discrepancies, thereby creating a final functional design F_final.
The more realistically the behavior of the functional design can be simulated in logic verification step 320, the less likely expensive downstream redesigns will be required. Therefore, during logic verification step 320, electrical rules (e.g., propagation delays, loading impedance) generated by a foundry as part of process development step 390 are often incorporated into the functional design to improve the accuracy of the simulation efforts. These electrical rules typically relate to basic process properties (e.g., interconnect resistance, parasitic capacitance) and are therefore available relatively early in the process development flow.
Unfortunately, details regarding physical effect characteristics are generally not available until much later in the process development flow. Physical effects are typically much more sensitive than basic electrical rules to small process adjustments, and therefore are not fully characterized until the process itself is relatively mature. Therefore, it is not feasible to incorporate physical effects into the logic simulation performed in logic verification step 320. Furthermore, even if the physical effect characteristics were available at this point, incorporating such details into the logic simulations might still be problematic, since the complex nature of such effects would result in a substantial increase the complexity of the models and the associated simulation runtimes.
Once the functional design is complete, the physical layout of the IC is generated in a place and route step 330. Using design rules Rdesign from process development step 390 that provide geometrical constraints and requirements for the placement of structures within the IC, an initial layout L_initial is created. Initial layout L_initial is a physical representation of the IC design. The accuracy and process compatibility of this layout is checked in a layout verification step 340, which can comprise design rule checking (DRC) and electrical rule checking (ERC) using design rules Rdesign and electrical rules Relec, respectively. Layout verification step 340 can also include a layout versus schematic (LVS) test to ensure that the physical layout matches the functional logic design (F_final). Over the course of layout verification step 340, any layout problems (e.g., rule violations, layout discrepancies) are corrected to generate a final design layout L_final, which is subsequently output in a tapeout step 350 as a set of basic layout data files D_layout.
Next, in an optical proximity correction (OPC) step 360, OPC features are added to the basic layout defined by layout data files D_layout to generate a corrected mask layout set M_layout. The OPC features, such as hammerheads, serifs, and assist features, are designed to “precompensate” for distortions that are produced by lithography and etch process steps, thereby improving the accuracy with which the design layout is implemented in the actual IC. OPC features are therefore based in large part on process characteristics Pchar determined during process development step 390.
A lithography mask set M_set is then created from corrected mask layout set M_layout in a mask production step 370. Mask set M_set is then used in a bench testing step 380 to produce test articles of the final IC. If those test articles satisfy the original IC specification, IC production can commence in full. Unfortunately, physical effects that have not been dealt with up until this point can prevent the test articles from meeting the requirements of the IC specification. When such problems are discovered, conventional responses are either to tune the process or to redesign the IC in an effort to eliminate or minimize the impact of the physical effects.
If the process defined in process development step 390 can be tuned to reduce the severity of physical effects, expensive IC design changes can be avoided. However, such tuning adds an additional layer of complexity onto what is already an extremely difficult task. By imposing additional process performance requirements, the already lengthy process development period can be significantly increased. This can lead to a delay in introducing a product to the market, which can have severe impact on profitability. Furthermore, some or all of the problematic physical effects may not even be addressable by adjusting the process, in which case any such tuning efforts would be wasted. Therefore, attempting to compensate for physical effects via process tuning is a problematic approach.
Therefore, an IC redesign (indicated by the dashed line between bench testing step 380 and logic design step 310) typically provides a more reliable corrective action for physical effects than does process tuning. However, once tapeout step 350 is complete, the IC design is essentially frozen. Subsequent design changes (e.g., modifying device locations, adding delay elements) require that the time-consuming, and hence costly, simulations of logic verification step 320 and layout verification step 340 be re-run with the modified design. Therefore, redesigning the IC at this point to compensate for physical effects is also problematic.
Accordingly, it is desirable to provide a system and method for compensating for physical effects that does not introduce excessive production delays and can be incorporated into the normal IC design and process development flows.